The present invention is generally directed to digital signal processors and, in particular, to an interface circuit that multiplexes and synchronizes multiple serial data streams from unsynchronized clock domains.
There are many applications in which it is necessary to combine unsynchronized data streams from different clock domains for subsequent processing by the same device. For example, in many communication devices (e.g., switches, routers, transceivers) a single digital signal processor (DSP) may be used to process multiple packet-based input serial data streams from unsynchronized clock domains. If the input streams are handled separately, the DSP incurs a delay whenever the DSP switches between domains and the input serial data stream in the new domain is not yet completely received. Conventional solutions to such problems often require synchronization of the clocks in the different clock domains.
Therefore, there is a need in the art for improved interface circuits for combining two or more input serial data streams from unsynchronized clock domains into a single contiguous output data stream. In particular, there is a need for an interface circuit that is capable of multiplexing together two or more input serial data streams without adding special timing synchronization circuitry.
To address the above-discussed deficiencies of the prior art, it is a primary object of the present invention to provide a serial stream interface for combining a master serial data stream comprising a sequence of N-bit master data packets and a slave serial data stream comprising a sequence of N-bit slave data packets. According to an advantageous embodiment of the present invention, the serial stream interface comprises: 1) a slave input interface comprising a slave buffer having a serial input for receiving the slave serial data stream and an N-bit slave parallel output for outputting each of the N-bit slave data packets, wherein the slave buffer stores the each N-bit slave data packet using at least one slave timing signal associated with the slave serial data stream; 2) a source selection circuit having a first input channel capable of receiving an N-bit master parallel output from a first master data source and a second input channel coupled to the N-bit slave parallel output; and 3) a serialization circuit having an input coupled to an output of the source selection circuit capable of receiving a selected one of the N-bit master parallel output and the N-bit slave parallel output and a serial output, wherein the serialization circuit sequentially shifts out each bit of the selected one of the N-bit master parallel output and the N-bit slave parallel output.
According to one embodiment of the present invention, each bit in each N-bit slave data packet stored in the slave buffer becomes available in the N-bit slave parallel output substantially concurrently with storage of each bit in the slave buffer.
According to another embodiment of the present invention, the slave buffer is a first-in, first-out (FIFO) device.
According to still another embodiment of the present invention, the slave buffer is a 1xc3x97N-bit random access memory (RAM).
According to yet another embodiment of the present invention, the slave input interface further comprises a slave control circuit capable of receiving the at least one slave timing signal and generating therefrom at least one storage control signal capable of storing the each of the N-bit slave data packets in the slave buffer.
According to a further embodiment of the present invention, the source selection circuit comprises a first multiplexer having an M-bit output.
According to a still further embodiment of the present invention, the serialization circuit comprises a second multiplexer having a first M-bit input channel coupled to the M-bit output of the first multiplexer.
According to a yet further embodiment of the present invention, the serialization circuit comprises a flip-flop circuit having an M-bit input coupled to an M-bit output of the second multiplexer, wherein the flip-flop latches M-bits of data received from the second multiplexer on an M-bit output of the flip-flop.
In one embodiment of the present invention, the second multiplexer further comprises a second M-bit input channel coupled to the M-bit output of the flip-flop.
The foregoing has outlined rather broadly the features and technical advantages of the present invention so that those skilled in the art may better understand the detailed description of the invention that follows. Additional features and advantages of the invention will be described hereinafter that form the subject of the claims of the invention. Those skilled in the art should appreciate that they may readily use the conception and the specific embodiment disclosed as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the invention in its broadest form.
Before undertaking the DETAILED DESCRIPTION OF THE INVENTION below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms xe2x80x9cincludexe2x80x9d and xe2x80x9ccomprise,xe2x80x9d as well as derivatives thereof, mean inclusion without limitation; the term xe2x80x9cor,xe2x80x9d is inclusive, meaning and/or; the phrases xe2x80x9cassociated withxe2x80x9d and xe2x80x9cassociated therewith,xe2x80x9d as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like; and the term xe2x80x9ccontrollerxe2x80x9d means any device, system or part thereof that controls at least one operation, such a device may be implemented in hardware, firmware or software, or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior, as well as future uses of such defined words and phrases.